(a) Technical Field
This application relates to an apparatus and a method for slicing an ingot. More particularly, the present invention relates to an apparatus and a method for slicing an ingot capable of improving fine unevenness of a wafer, i.e., its nanotopography.
(b) Description of the Related Art
Generally, a wafer manufacturing process includes an ingot growing process, a slicing process, an edge grinding process, a lapping process, an etching process, a back side polishing process, a pre-anneal cleaning process, an edge polishing process, and a front polishing process. In the ingot growing process, silicon (Si) is induced from sand and is then purified to make a silicon raw material. A desired impurity is then injected to make an N-type or P-type silicon ingot. In the slicing process, the N-type or P-type silicon ingot produced in the ingot process is cut to have a desired thickness. In the edge grinding process, in order to reduce the roughness and to have a predetermined shape at an edge portion of the wafer that is caused by the slicing process, the edge portion of the wafer is polished. In the lapping process, in order to improve the flatness on the front and back surfaces of the wafer that have been cut to a given thickness, the surfaces of the wafer are polished. In the etching process, in order to remove remaining fine cracks or defects on the surface of the wafer that is polished in the lapping process, the surface of the wafer is etched using a chemical reaction. In the back side polishing process, in order to improve the flatness of the back side surface of the wafer and to remove damage thereof caused by the etching process, the back side surface of the wafer is polished. In the pre-anneal cleaning process, in order to compensate for an incomplete lattice defect structure occurring on the surface that is caused by the etching process, annealing and cleaning processes are performed on the surface of the wafer. In the edge polishing process, in order to reduce surface damage and poor flatness at the edge portion of the wafer caused by the etching process, the edge portion of the wafer is polished. Finally, in the front polishing process, in order to repair damage and improve the flatness of the front side of the wafer occurring by the etching process, the front side of the wafer is polished.
As described above, the wafer manufacturing process produces a polished wafer by successively performing the ingot growing process, the slicing process, the lapping process, the etching process, and the polishing processes. More specifically, in the slicing process, an ingot made in the ingot growing process is cut into thin sheets using a cutting tool. In the cutting tool, a highly tensioned steel wire is wound around a plurality of grooved rollers with a predetermined pitch, and slurry is supplied to the wire. The wire is carried over the grooved rollers along one direction or in a reciprocative manner at high speed. The ingot is pressed onto the wire at a predetermined speed, while the slurry is supplied to the wire.
Due to the cutting force of the wire, the ingot is sliced into thin sheets of wafer via the slurry.
In the slicing process, the wire and the ingot are formed with a circular section of a predetermined diameter and a feed rate is varied to be high at the beginning and end points of slicing and low at the middle point, wherein a feed rate refers to a feed speed at which the ingot is supplied onto the wire. Accordingly, at the beginning of slicing, it is difficult for the wire to be positioned at a desired position of the ingot. As a result, the sliced wafer may have undesirably high nanotopography at one or more surface portions thereof, even after successively having achieved the lapping process, the etching process, and the polishing processes. High nanotopography generally causes a low yield rate of semiconductor chips.
The nanotopography refers to a nanometer scale height variation or an unevenness of a spatial wave produced on a surface of a wafer; roughness refers to an A scale height variation, and flatness refers to a μm scale height variation in order to indicate fine surface characteristics. It is desired to develop a design rule capable of preventing poor nanotopography in the development of semiconductor technology. A design rule has been developed to improve fine surface characteristics of a wafer, that is, a nanometer scale wave depending on a chemical and mechanical composite polishing process referred to as CMP (Chemo-Mechanical Polishing). This process has been adapted to meet objectives of the slicing process using the wire in the wafer manufacturing process.
In the slicing process, the use of a conventional wire to slice the ingot causes poor nanotopography, that is, spatial waves on a surface of a wafer. When the sliced wafer has high nanotopography, many failed products are produced even after successively having achieved the lapping process, the etching process, and the polishing processes.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.